1. Field of the Invention
This invention relates generally to a technique for connecting multiple semiconductor devices in a single configuration, and more particularly to a technique for mounting multiple high power metal oxide field effect transistors (MOSFETS) in a single configuration that eliminates internal oscillations while maximizing device performance such as gain, bandwidth, etc. while reducing package complexity.
2. Brief Description of the Prior Art
The desire for high power semiconductor devices has led manufacturers to combining multiple die in a single package in such a way that the package has the characteristics of a single semiconductor device. This precedent has long been established in devices designed to run at higher frequencies. While lower frequency applications have driven device manufactures to make larger single die to handle higher power densities, high frequency applications favor parallel combinations of smaller die to maximize device performance and better control power dissipation at the intended frequency of use. It has been found that these devices may be subject to internal oscillations. Such as when four transistor die are combined, two die or two pairs of die can oscillate 180 degrees out of phase, three die can oscillate 120 degrees out of phase, or four die can oscillate 90 degrees out of phase. As a result the external connections act as virtual grounds and nothing that is done external to the package can prevent the internal oscillations when the device is biased in its active region. This problem is known, though more often solved by placing resistors in the gate of combined MOSFET devices to prevent the oscillations, though at the expense of device performance. Most MOSFET packages which utilize multiple combined die benefit from a very low impedance source connection which is generally connected directly to the amplifier ground. This physical connection will be shown to enable greater stability, allowing some packages to eliminate the gate resistors altogether. As new topologies in use at higher frequencies begin to take advantage of higher voltage and higher speed devices, power semiconductor packages are required to be isolated from the local ground source. Existing semiconductor packages which combine multiple die and newer ones which utilize similar die-interconnect methods with their grounded-source predecessors would now suffer from instabilities, forcing a solution which compromises device performance to resolve. A similar problem is developing in lower frequency semiconductor devices. Although these devices are typically isolated to begin with, issues with increasing power cycling requirements have called for smaller multiple combined die to replace the existing larger single die, now creating internal oscillations that had not previously been noted. Although utilization of high frequency oscillation dampening methods, including gate resistors, may not notably affect device performance, it does increase the package complexity, and therefore cost.
One example of a prior art packaging design is shown in FIG. 1. In FIG. 1 there is shown field effect transistor (FET) die 2,4,6, and 8 that are mounted in a single package generally shown as 10. The package consists of a ceramic base 12 providing a supporting structure and metallizations 14 shown hashed which forms the interconnects. The package consists of one gate terminal 16 and four separate source terminals 18, 20, 22, and 24, which are connected in pairs. Terminal 18 is connected to terminal 20 and terminal 22 is connected to 24 by the metallizations on the ceramic base 12. No internal connection is made between the terminals 18 and 22. Also shown are four source resistors 26, 28, 30, and 32 connected to the die by wire bonds such as 34. As will be shown herein after, because there is no low inductance connection between the source of each die and the first point where the sources are connected together, internal oscillations can result with the FET pairs 2-4 and 6-8 taking part in the oscillation. The package of this design is especially vulnerable to internal oscillations if the source is not grounded, i.e. allowed to float as is frequently required. In a floating source design the inductance between the two groups of source terminals 18-20 and 22-24 can be high enough to cause the internal oscillations described herein.
Another example of a prior art packaging technique is shown in FIG. 2. This example has two die 36 and 38 on a ceramic insulator 40. The gate distribution network 42 runs along the center of the package and two source connections 44 and 46 are on the edges of the package. Although the source wire bonds such as 48 connect the two die, the high inductance of this connection necessitates the connection of the source terminals 44 and 46 to the conducting base 50 through conductive strips 52 along the side of the package. Designs like this, which has the gate along the middle of the configuration of devices, is fairly typical of prior art designs. This is also found in U.S. Pat. No. 6,020,636 issued to G. C. Adishian wherein the gates are arranged in the geometric center of the configuration and the sources connected along the outside. In this case gate resistors are utilized.
Since the external gate, drain and source connections act as virtual grounds when the configuration of devices oscillate internally, the oscillations can be analyzed by considering the equivalent circuit of a single device taking part in the oscillation. A linearized model is good enough to explain the onset of oscillations and the methods required to prevent such oscillations, which is the object of the present invention. A model of a single die (or a group of die acting in concert) with parasitic components and the transformations required to obtain a simple circuit from which to determine the loop gain is shown in FIG. 3. In FIG. 3(a) the linearized current gain (change in drain to source current over the change in gate to source voltage) of a single die is denoted by h. The gate, drain and source terminals are labeled g, d, and s respectively. C1, C2 and C3 represent the linearized incremental gate-drain, gate-source and drain-source capacitances, respectively. R3 represents the gate resistance. The parasitic inductance, bond wires and interconnect, between the die and the point where the gates of the various die are first connected together is represented by L3 and the parasitic inductance between the source and the point where the sources are first connected together is represented by L2. The drain inductance is ignored in this analysis, as it is usually small. By transforming the circuit as shown in FIG. 3(b), the loop gain is simply the voltage at the gate (g). In FIG. 3(b) AC=h indicates an independent sinusoidal current source with amplitude h. A typical set of parameters is shown in Table 1.
With typical parameters like these, the following critical observation is made. If the phase of the loop gain is plotted vs. frequency and L3 is varied, there is a critical value of L3 at which the phase change at resonance changes from a destabilizing to a stabilizing phase change.
Having a phase that is stabilizing for all values of gain is a big advantage as the gain can vary considerably depending on how the device is biased. The principle at stake is that the frequency at which the gate inductance resonates with the gate-drain capacitance must be low in relation to the frequency at which the drain-source capacitance resonates with the source inductance. This is demonstrated in FIGS. 4-8.
FIG. 4 illustrates the phase of the loop gain with a gate inductance L3 equal to 8 nH.
FIG. 5 illustrates the phase of the loop gain with a gate inductance L3 equal to 12 nH.
FIG. 6 illustrates the phase of the loop gain with a gate inductance L3 equal to 22 nH.
FIG. 7 illustrates the phase of the loop gains for gate inductances L3 of 8, 12, and 22 nH. FIG. 8 Illustrates the magnitude of the loop gains for gate inductances of 8, 12, and 22 nH. Note that these magnitudes are for a current gain of 2, so they can increase by as much as 30 dB from these values for typical devices. Since the bias affects the exact values of the linearized capacitances, some margin is desired.
The linearized equivalent circuit of FIG. 3 is sufficient for illustrating the two parallel resonances and the effect on stability. A slightly more detailed equivalent circuit is shown in FIG. 9. Using this circuit the subset of the closed loop poles with respect to a disturbance that can possibly have positive real parts can be calculated as a function of the gate inductance.
The subset of pole positions referred to above, as a function of gate inductance is shown in FIG. 10. The closed loop positions are plotted as a function of the gate inductance where C1=50 pF, C2=1.45 nF, C3=100 pF, R1=0.2xcexa9, L1=0.1 nH, R2=0.4xcexa9, L2=6 nH, R3=1.5xcexa9, and h=6 A/V. h is the linearized current gain which is the change in drain to source current divided by the change in gate to source voltage. FIG. 11 illustrates a close up view of the closed loop pole positions as a function of the gate inductance.
In configurations of devices where multiple devices are combined to act as a single device, there is usually a gate distribution network of some sort to electrically connect the gate terminals of each device to a common gate connection. The analysis shows that inductance between the gate terminal of each die and the point where the gate terminals of the die are first connected together can prevent internal oscillations. The inductance of the gate distribution network from the point where the gate terminals are first connected together to the common gate connection has no effect on the stability of the configuration with respect to internal oscillations. Many prior art configurations of devices have sufficient gate inductance because either the source inductance is small enough so that very little gate inductance is required, or the inductance of the gate bond wires provide sufficient inductance. However when more and or larger die are combined in configurations where low impedance connections between the sources of all devices are impractical, the gate bond wires no longer provide adequate gate inductance. In the design of isolated configurations of devices, i.e. configurations in which the source terminal is not intended to be connected to the local ground reference, prior art configurations have difficulty in achieving low impedance connections between the sources of all devices. This is because in larger configurations the source connections are traditionally placed facing the perimeter of the configuration allowing a low inductance connection to the local ground reference.
It would be desirable if there were provided a configuration for combining multiple FETs for switching high frequency, high power applications that did not have internal oscillations and at the same time does not degrade the performance of the configuration.
It is an object of this invention to design an effective configuration for combining multiple FETs by changing the gate inductances of each device to eliminate internal oscillations without increasing, or only slightly increasing, the external inductance of the configuration.
There is provided by this invention a configuration for combining multiple MOSFET devices for high power, high frequency applications that prevents internal oscillations. Stability of the configuration is obtained by increasing the inductance between the gate of each device in the configuration and the point where the gates are first connected together. The gate distribution network for the multiple devices are split such that each MOSFET die has an individual gate feed that are subsequently connected at a common point. The sequence at which the gate and source resonances occur within the configuration is manipulated in order to ensure stability. Such manipulation may also include unusual configurations to ensure very low inductance between the source of each die and the point where the sources are first connected together.